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|Title:||Delay Analysis of neuron-MOS and Capacitive Threshold-Logic|
|Citation:||ICECS 2000 : The 7th IEEE International Conference On Electronics, Circuits & Systems, December 17-20, 2000 Jounieh, Lebanon; volume 2: pp. 932-935|
|Publisher:||The Institute of Electrical and Electronics Engineers, Inc.|
|Conference Name:||IEEE International Conference on Electronics, Circuits, and Systems (7th : 2000 : Jounieh, Lebanon)|
|Peter Celinski, Said Al-Sarawi, and Derek Abbott|
|Abstract:||A model for the delay of neuron-PMOS (neu-MOS) and Capacitive Threshold-Logic (CTL) based logic circuits is presented for the first time. It is based on the analysis of the basic neuron-MOS and CTL gate structures. A closed form analytic expression for the delay of the threshold gate is derived. A relation for the delay in terms of an ordinary CMOS inverter delay expressed as a function of the number of inputs to the threshold gate is presented. This relation is shown to be useful in comparing the delay of logic circuit designs based on neu-MOS or CTL and ordinary CMOS.|
|Keywords:||neuron-MOS; capacitive-threshold logic; floating gate transistor|
|Rights:||Copyright © 2000 by The Institute of Electrical and Electronics Engineers, Inc. All rights reserved.|
|Appears in Collections:||Electrical and Electronic Engineering publications|
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