Please use this identifier to cite or link to this item: https://hdl.handle.net/2440/68318
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Type: Journal article
Title: High-speed full adder based on minority function and bridge style for nanoscale
Author: Navi, K.
Sajedi, H.
Mirzaee, R.
Moaiyeri, M.
Jalali, A.
Kavehei, O.
Citation: Integration, 2011; 44(3):155-162
Publisher: Elsevier Science BV
Issue Date: 2011
ISSN: 0167-9260
1872-7522
Statement of
Responsibility: 
Keivan Navi, Horialsadat Hossein Sajedi, Reza Faghih Mirzaee, Mohammad Hossein Moaiyeri, Ali Jalali and Omid Kavehei
Abstract: In this paper a new high-speed and high-performance Full Adder cell, which is implemented based on CMOS bridge style and minority function, is proposed. Several simulations conducted at nanoscale using different power supplies, load capacitors, frequencies and temperatures demonstrate the superiority of the proposed design in terms of delay and power-delay product (PDP) compared to the other cells. In addition the proposed structure improves the robustness and reduces sensitivity to the process variations of the other Bridge-Cap Full Adder cell already presented in the literature. © 2011 Elsevier B.V. All rights reserved.
Keywords: Full adder
Minority function
Bridge style
High-speed
Nanoelectronics
Process variation
Rights: Copyright © 2011 Elsevier B.V. All rights reserved.
DOI: 10.1016/j.vlsi.2011.01.003
Published version: http://dx.doi.org/10.1016/j.vlsi.2011.01.003
Appears in Collections:Aurora harvest
Electrical and Electronic Engineering publications

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