Estimating adders for a low density parity check decoder
Date
2006
Authors
Phillips, B.
Kelly, D.
Ng, B.
Editors
Luk, F.
Advisors
Journal Title
Journal ISSN
Volume Title
Type:
Conference paper
Citation
Advanced Signal Processing Algorithms, Architectures, and Implementations XVI / F.T. Luk (ed.) pp. 631302 1-9 [electronic resource]
Statement of Responsibility
Braden J. Phillips, Daniel R. Kelly, and Brian W. Ng
Conference Name
Advanced Signal Processing Algorithms, Architectures, and Implementations XVI (2006)
Abstract
Low density parity check decoders use computation nodes with multioperand adders on their critical path. This paper describes the design of estimating multioperand adders to reduce the latency, power and area of these nodes. The new estimating adders occasionally produce inaccurate results. The effect of these errors and the subsequent trade-off between latency and decoder frame error rate is examined. For the decoder investigated it is found that the estimating adders do not degrade the frame error rate.
School/Discipline
Dissertation Note
Provenance
Description
Copyright 2006 Society of Photo-Optical Instrumentation Engineers.