Approximate signed binary integer multipliers for arithmetic data value speculation

Simple item page
dc.contributor.authorKelly, D.
dc.contributor.authorPhillips, B.
dc.contributor.authorAl-Sarawi, S.
dc.contributor.conferenceConference on Design & Architectures For Signal And Image Processing (2009 : Sophia Antipolis, France)
dc.contributor.editorMarco Mattavelli,
dc.date.issued2009
dc.description.abstractArithmetic data value speculation increases the throughput of a processor pipeline by speculatively issuing the dependent operations of an arithmetic operation based on the early arrival of an approximate result. Suitable approximate multipliers calculate a product faster than an exact multiplier, with an associated probability that the approximate product is correct. This paper presents the design of a family of signed approximate multipliers for use in a speculative data path. A signed 32x32 bit multiplier synthesised with the TSMC Artisan 180nm SAGE-X™ cell library is found to be 20% faster than a full-adder based tree multiplier, with a probability of error less than 14% for benchmark applications.
dc.description.statementofresponsibilityDaniel R. Kelly, Braden J. Phillips and Said Al-Sarawi
dc.description.urihttp://www.ecsi.org/resource/approximate-signed-binary-integer-multipliers-arithmetic-data-value-speculation
dc.identifier.citationProceedings of the 2009 Conference on Design & Architectures For Signal And Image Processing / M. Mattavelli (ed.): pp.97-104
dc.identifier.orcidPhillips, B. [0000-0001-8288-4791]
dc.identifier.orcidAl-Sarawi, S. [0000-0002-3242-8197]
dc.identifier.urihttp://hdl.handle.net/2440/64509
dc.language.isoen
dc.publisherECSI
dc.publisher.placeonline
dc.rightsCopyright status unknown
dc.source.urihttp://www.ecsi.org/sites/default/files/rs5.1.pdf
dc.titleApproximate signed binary integer multipliers for arithmetic data value speculation
dc.typeConference paper
pubs.publication-statusPublished

Files

Collections

Electrical and Electronic Engineering publications