Electrical Reliability Due to Offset Gate in Triple Polysilicon Flash EEPROM Cell
| dc.contributor.author | Hariz, A.J. | |
| dc.contributor.author | Kim, Y.S. | |
| dc.contributor.author | Kim, N.S. | |
| dc.date.issued | 1999 | |
| dc.identifier.citation | Journal of Electrical Engineering and Information Science, 1999 | |
| dc.identifier.issn | 1226-1262 | |
| dc.identifier.uri | https://hdl.handle.net/1959.8/130443 | |
| dc.language.iso | en | |
| dc.publisher | Korea Institute of Communication Sciences | |
| dc.title | Electrical Reliability Due to Offset Gate in Triple Polysilicon Flash EEPROM Cell | |
| dc.type | Journal article | |
| pubs.publication-status | Published | |
| ror.mmsid | 9915912189001831 |