Introducing 32 nm technology in Microwind35
Date
2010
Authors
Sicarde, E.
Aziz, S.M.
Editors
Advisors
Journal Title
Journal ISSN
Volume Title
Type:
Report
Citation
Statement of Responsibility
Conference Name
Abstract
This paper describes the improvements related to the CMOS 32 nm technology and the implementation of this technology in Microwind35. The main novelties related to the 32 nm technology such as the high-k gate oxide, 3rd generation channel strain, metal-gate and very low-K interconnect dielectric is described. The performances of a ring oscillator layout and a 6-transistor RAM memory layout are also analyzed.
School/Discipline
Dissertation Note
Provenance
Description
Access Status
Rights
Copyright 2010 32 nm technology