Resource efficient flexible architectures for low-density parity-check decoders /
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(Published version)
Date
2012
Authors
Chandrasetty, Vikram Arkalgud,
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Journal Title
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Type:
thesis
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Abstract
Low-Density-Parity-Check (LDPC) codes are very attractive for error correction in data communication. Hardware implementation of large LDPC decoders is still a challenge due to huge complexity and high resource requirement. This thesis proposes innovative techniques to reduce the complexity of LDPC decoding algorithms without affecting performance. It also presents a methodology to construct flexible LDPC codes that are suitable for designing resource efficient hardware architectures. Based on the low-complexity algorithms and codes developed, the thesis presents the design of partially-parallel decoders with scalable throughput. The proposed decoders have been implemented on Field Programmable Gate Arrays (FPGA) for multiple wireless application standards. Thus, the thesis addresses some of the challenges associated with the practical implementation of high performance LDPC decoders.
School/Discipline
University of South Australia. School of Electrical and Information Engineering.
School of Electrical and Information Engineering
School of Electrical and Information Engineering
Dissertation Note
Thesis (PhD)--University of South Australia, 2012.
Provenance
Copyright 2012 Vikram Arkalgud Chandrasetty.
Description
1 ethesis (xxiv, 148 pages) :
colour illustrations.
Includes bibliographical references: p. 129-137.
colour illustrations.
Includes bibliographical references: p. 129-137.
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