FPGA implementation of high performance LDPC decoder using modified 2-bit min-sum algorithm
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(Published version)
Date
2010
Authors
Arkalgud Chandrasetty, V.
Aziz, S.M.
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Conference paper
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Proceedings of the 2nd international conference on computer research and development (ICCRD 2010), 2010, iss.5489454, pp.881-885
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2nd International Conference on Computer Research and Development (ICCRD 2010) (7 May 2010 - 10 May 2010 : Kuala Lumpur, Malaysia)
Abstract
In this paper, a reduced complexity Low-Density Parity-Check (LDPC) decoder is designed and implemented on FPGA using a modified 2-bit Min-Sum algorithm. Simulation results reveal that the proposed decoder has improvement of 1.5 dB Eb/No at 10-5 bit error rate (BER) and requires fewer decoding iterations compared to original 2-bit Min-Sum algorithm. With a comparable BER performance to that of 3- bit Min-Sum algorithm, the decoder implemented using modified 2-bit Min-Sum algorithm saves about 18% of FPGA slices and can achieve an average throughput of 10.2 Gbps at 4 dB Eb/No.
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