A-DELTA: A 64-bit high speed, compact, hybrid dynamic-CMOS/threshold-logic adder
Date
2003
Authors
Celinski, P.
Cotofana, S.
Abbott, D.
Editors
Mira, J.
Alvarez, J.R.
Alvarez, J.R.
Advisors
Journal Title
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Journal article
Citation
Lecture Notes in Computer Science (including subseries Lecture Notes in Artificial Intelligence and Lecture Notes in Bioinformatics), 2003; 2687:73-80
Statement of Responsibility
Peter Celinski, Sorin D. Cotofana and Derek Abbott
Conference Name
Abstract
A high speed 64-bit dynamic adder, the Adelaide-Delft Threshold Logic Adder (A-DELTA), is presented. The adder is based on a hybrid carry-lookahead/carry-select scheme using threshold logic and conventional CMOS logic. A-DELTA was designed and simulated in a 0.35 pm process. The worst case critical path latency is 670 ps, which is shown to be on average 30% faster than previously proposed high speed Boolean dynamic logic adders while at the same time reducing the transistor count on average by over 30% compared to the same adders.
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Description
The original publication is available at www.springerlink.com