A synthesisable VHDL model for an easily testable generalised multiplier
Date
2002
Authors
Aziz, S.M.
Basheer, C.N.
Kamruzzaman, J.
Editors
Renovell, M.
Kaijihara, S.
AlBahadly, I.
Demidenko, S.
Kaijihara, S.
AlBahadly, I.
Demidenko, S.
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Conference paper
Citation
Proceedings of the 1st International Workshop on Electronic Design, Test and Applications, 2002 / Renovell, M., Kaijihara, S., AlBahadly, I., Demidenko, S. (ed./s), pp.504-506
Statement of Responsibility
Conference Name
1st IEEE International Workshop on Electronic Design, Test and Applications (29 Jan 2002 - 31 Jan 2002 : Christchurch, New Zealand)
Abstract
This paper presents a synthesisable VHDL model for a generalised multiplier capable of performing multiplication of both sign-magnitude and two's complement operands. The multiplier is testable with a constant number of test vectors irrespective of operand word-lengths thereby reducing automatic test generation, simulation and testing times. The model has been used successfully for generating multiplier macros of various operand lengths in different target technologies. A test generation program has been developed for automatic generation of vectors of variable lengths.
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