On C-testability on carry free dividers
Date
2002
Authors
Aziz, S.M.
Carr, S.J.
Editors
Renovell, M.
Kaijihara, S.
AlBahadly, I.
Demidenko, S.
Kaijihara, S.
AlBahadly, I.
Demidenko, S.
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Conference paper
Citation
1st IEEE International Workshop on Electronic Design, Test and Applications, 2002 / Renovell, M., Kaijihara, S., AlBahadly, I., Demidenko, S. (ed./s), pp.417-421
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Conference Name
1st IEEE International Workshop on Electronic Design, Test and Applications (29 Jan 2001 - 31 Jan 2002 : Christchurch, New Zealand)
Abstract
This paper examines the C-testability of a carry-free divider architecture that uses a radix-2 number system. This divider is extremely fast in comparison to the traditional carry-propagate method of division. It has a computational time of the order of O(W), while carrypropagate division has a time of the order of O(W2). The results of the investigation presented here show that the architecture requires the addition of a significant amount of logic circuitry for correct functionality and uniformity of the inputs and outputs. This paper presents the logic blocks required to turn the architecture into one that can be implemented in hardware and examines the effects of these changes on the computation time and testability.
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