Hybrid parallel counters - Domino and threshold logic
Date
2004
Authors
Townsend, T.
Celenski, P.
Al-Sarawi, S.
Liebelt, M.
Editors
Smailagic, A.
Bayoumi, M.
Bayoumi, M.
Advisors
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Type:
Conference paper
Citation
IEEE Computer Society Annual Symposium on VLSI : proceedings : Emerging trends in VLSI systems design / Asim Smailagic and Magdy Bayoumi (eds.):pp.275-276
Statement of Responsibility
Troy D. Townsend, Peter Celinski, Said F. Al-Sarawi and Michael J. Liebelt
Conference Name
IEEE Computer Society Symposium on VLSI (2004 : Lafayette, Louisiana)
Abstract
Parallel counters are the building blocks of partial product reduction tree (PPRT) circuits, which are required for high-performance multiplication. In this paper we will implement novel counters using a hybrid of domino and threshold logic. A test 64 × 64 PPRT using these counters was found to reduce latency by 39% and device count by 38% compared to the domino logic equivalent.
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Description
Copyright © 2004 IEEE