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New structure for adder with improved speed, area and power

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dc.contributor.authorKarami H, F.
dc.contributor.authorKarami Horestani, A.
dc.contributor.conferenceIEEE International Conference on Networked Embedded Systems for Enterprise Applications (2nd : 2011 : Fremantle, WA)
dc.date.issued2011
dc.description.abstractAdders are the main parts of processing circuits and play an important role in all mathematical operations like subtraction, multiplication, division, etc. Carry Look ahead Adder (CLA) is one of the fastest adder structures that is widely used in the processing circuits. In this article a new structure for adder is proposed. The results show that compared to the previous common Modified Carry Look ahead Adder (MCLA) structure, the proposed structure has very smaller on-chip area and delay and also it has lower power consumption. Using the proposed structure a 64-bit adder is designed and results are presented. The circuit is designed in TSMC 0.18μm CMOS technology with 1.8v power supply and simulated with HSPICE.
dc.description.statementofresponsibilityFatemeh Karami H. and Ali K. Horestani
dc.identifier.citationProceedings of the IEEE 2nd International Conference on Networked Embedded Systems for Enterprise Applications, held in Perth, Western Australia, 8-9 December, 2011 / D. Hughes, K. Lee and K.L. Man (eds.), pp.1-6
dc.identifier.doi10.1109/NESEA.2011.6144953
dc.identifier.isbn9781467304955
dc.identifier.urihttp://hdl.handle.net/2440/71309
dc.language.isoen
dc.publisherIEEE
dc.publisher.placeUSA
dc.rights© 2011 IEEE
dc.source.urihttp://dx.doi.org/10.1109/nesea.2011.6144953
dc.titleNew structure for adder with improved speed, area and power
dc.typeConference paper
pubs.publication-statusPublished

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