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Please use this identifier to cite or link to this item: https://hdl.handle.net/2440/45036
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dc.contributor.authorLim, Z.-
dc.contributor.authorPhillips, B.-
dc.contributor.editorMatthews, M.B.-
dc.date.issued2007-
dc.identifier.citationACSSC 2007: Conference Record of the Forty-First Asilomar Conference on Signals, Systems and Computers:pp.1430-1434-
dc.identifier.isbn9781424421107-
dc.identifier.issn1058-6393-
dc.identifier.urihttp://hdl.handle.net/2440/45036-
dc.description.abstractThis paper presents a new residue number system implementation of the RSA cryptosystem. The system runs on a low-area, low-power microprocessor that we have extended with hardware support for residue arithmetic. When compared against a baseline implementation that uses non-RNS multi-precision methods, the new RNS implementation executes in 67.7% fewer clock cycles. The hardware support requires 42.7% more gates than the base processor core. © 2007 IEEE.-
dc.language.isoen-
dc.publisherIEEE-
dc.source.urihttp://dx.doi.org/10.1109/acssc.2007.4487465-
dc.titleAn RNS-enhanced microprocessor implementation of public key cryptography-
dc.typeConference paper-
dc.contributor.conferenceAsilomar Conference on Signals, Systems & Computers (41st : 2007 : Pacific Grove, California)-
dc.identifier.doi10.1109/ACSSC.2007.4487465-
dc.publisher.placeCDROM-
pubs.publication-statusPublished-
dc.identifier.orcidPhillips, B. [0000-0001-8288-4791]-
Appears in Collections:Aurora harvest 6
Electrical and Electronic Engineering publications

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