Approximate signed binary integer multipliers for arithmetic data value speculation
Date
2009
Authors
Kelly, D.
Phillips, B.
Al-Sarawi, S.
Editors
Marco Mattavelli,
Advisors
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Type:
Conference paper
Citation
Proceedings of the 2009 Conference on Design & Architectures For Signal And Image Processing / M. Mattavelli (ed.): pp.97-104
Statement of Responsibility
Daniel R. Kelly, Braden J. Phillips and Said Al-Sarawi
Conference Name
Conference on Design & Architectures For Signal And Image Processing (2009 : Sophia Antipolis, France)
Abstract
Arithmetic data value speculation increases the throughput of a processor pipeline by speculatively issuing the dependent operations of an arithmetic operation based on the early arrival of an approximate result. Suitable approximate multipliers calculate a product faster than an exact multiplier, with an associated probability that the approximate product is correct. This paper presents the design of a family of signed approximate multipliers for use in a speculative data path. A signed 32x32 bit multiplier synthesised with the TSMC Artisan 180nm SAGE-X™ cell library is found to be 20% faster than a full-adder based tree multiplier, with a probability of error less than 14% for benchmark applications.
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