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|Title:||New structure for adder with improved speed, area and power|
|Author:||Karami H, F.|
Karami Horestani, A.
|Citation:||Proceedings of the IEEE 2nd International Conference on Networked Embedded Systems for Enterprise Applications, held in Perth, Western Australia, 8-9 December, 2011 / D. Hughes, K. Lee and K.L. Man (eds.), pp.1-6|
|Conference Name:||IEEE International Conference on Networked Embedded Systems for Enterprise Applications (2nd : 2011 : Fremantle, WA)|
|Fatemeh Karami H. and Ali K. Horestani|
|Abstract:||Adders are the main parts of processing circuits and play an important role in all mathematical operations like subtraction, multiplication, division, etc. Carry Look ahead Adder (CLA) is one of the fastest adder structures that is widely used in the processing circuits. In this article a new structure for adder is proposed. The results show that compared to the previous common Modified Carry Look ahead Adder (MCLA) structure, the proposed structure has very smaller on-chip area and delay and also it has lower power consumption. Using the proposed structure a 64-bit adder is designed and results are presented. The circuit is designed in TSMC 0.18μm CMOS technology with 1.8v power supply and simulated with HSPICE.|
|Rights:||© 2011 IEEE|
|Appears in Collections:||Electrical and Electronic Engineering publications|
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