Unbiased finite-memory digital phase-locked loop
| dc.contributor.author | You, S. | |
| dc.contributor.author | Pak, J. | |
| dc.contributor.author | Ahn, C. | |
| dc.contributor.author | Shi, P. | |
| dc.contributor.author | Lim, M. | |
| dc.date.issued | 2016 | |
| dc.description | Date of publication February 18, 2016; date of current version July 28, 2016 | |
| dc.description.abstract | Digital phase-locked loops (DPLLs) have been commonly used to estimate phase information. However, they exhibit poor performance or, occasionally, a divergence phenomenon, if noise information is incorrect or if there are quantization effects. To overcome the weaknesses of existing DPLLs, we propose a new DPLL with a finite-memory structure called the unbiased finite-memory DPLL (UFMDPLL). The UFMDPLL is independent of noise covariance information, and it shows intrinsic robustness properties against incorrect noise information and quantization effects due to the finite-memory structure. Through numerical simulations, we show that the proposed DPLL is more robust against incorrect noise information and quantization effects than the conventional DPLLs are. | |
| dc.description.statementofresponsibility | Sung Hyun You, Jung Min Pak, Choon Ki Ahn, Peng Shi, and Myo Taeg Lim | |
| dc.identifier.citation | IEEE Transactions on Circuits and Systems - II - Express Briefs, 2016; 63(8):798-802 | |
| dc.identifier.doi | 10.1109/TCSII.2016.2531138 | |
| dc.identifier.issn | 1549-7747 | |
| dc.identifier.issn | 1558-3791 | |
| dc.identifier.orcid | Shi, P. [0000-0001-6295-0405] [0000-0001-8218-586X] [0000-0002-0864-552X] [0000-0002-1358-2367] [0000-0002-5312-5435] | |
| dc.identifier.uri | http://hdl.handle.net/2440/106931 | |
| dc.language.iso | en | |
| dc.publisher | IEEE | |
| dc.relation.grant | http://purl.org/au-research/grants/arc/DP140102180 | |
| dc.relation.grant | http://purl.org/au-research/grants/arc/LP140100471 | |
| dc.relation.grant | http://purl.org/au-research/grants/arc/LE150100079 | |
| dc.rights | © 2016 IEEE. | |
| dc.source.uri | https://doi.org/10.1109/tcsii.2016.2531138 | |
| dc.subject | Digital phase-locked loop (DPLL); finite-memory structure; unbiasedness | |
| dc.title | Unbiased finite-memory digital phase-locked loop | |
| dc.type | Journal article | |
| pubs.publication-status | Published |