Simulations of modular multipliers on FPGA
Date
2007
Authors
Kong, Y.
Phillips, B.
Editors
Ma, H.
Advisors
Journal Title
Journal ISSN
Volume Title
Type:
Conference paper
Citation
Proceedings of Asian Modelling and Simulation / L. Miao (ed.): pp.128-131
Statement of Responsibility
Y. Kong and B. Phillips
Conference Name
IASTED Asian Conference on Modelling and Simulation (Oct. 2007 : Beijing, China)
Abstract
A diverse variety of algorithms and architectures for modu lar multiplication have been published. They were recently classified into four classes, i.e. Sum of Residues, Classical, Barrett and Montgomery. This paper provides timing and area results for FPGA implementations and a survey of the four different architectures and wordlengths.