Simulations of modular multipliers on FPGA

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dc.contributor.authorKong, Y.
dc.contributor.authorPhillips, B.
dc.contributor.conferenceIASTED Asian Conference on Modelling and Simulation (Oct. 2007 : Beijing, China)
dc.contributor.editorMa, H.
dc.date.issued2007
dc.description.abstractA diverse variety of algorithms and architectures for modu lar multiplication have been published. They were recently classified into four classes, i.e. Sum of Residues, Classical, Barrett and Montgomery. This paper provides timing and area results for FPGA implementations and a survey of the four different architectures and wordlengths.
dc.description.statementofresponsibilityY. Kong and B. Phillips
dc.description.urihttp://www.actapress.com/Abstract.aspx?paperId=31832
dc.identifier.citationProceedings of Asian Modelling and Simulation / L. Miao (ed.): pp.128-131
dc.identifier.isbn9780889867017
dc.identifier.orcidPhillips, B. [0000-0001-8288-4791]
dc.identifier.urihttp://hdl.handle.net/2440/44802
dc.language.isoen
dc.publisherIASTED
dc.publisher.placeCDROM
dc.subjectModular Multiplication
dc.subjectFPGA
dc.subjectSimulations
dc.subjectCryptography
dc.subjectE-Security
dc.titleSimulations of modular multipliers on FPGA
dc.typeConference paper
pubs.publication-statusPublished

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