Analysis of network-on-chip topologies for cost-efficient chip multiprocessors

Ortín-Obón, M.; Suárez-Gracia, D.; Villarroya-Gaudó, M.; Izu, C.; Viñals-Yúfera, V.

doi:10.1016/j.micpro.2016.01.005

Analysis of network-on-chip topologies for cost-efficient chip multiprocessors

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hdl_97927.pdf (567.85 KB)

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2016

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Ortín-Obón, M.

Suárez-Gracia, D.

Villarroya-Gaudó, M.

Izu, C.

Viñals-Yúfera, V.

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Journal article

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Microprocessors and Microsystems, 2016; 42:24-36

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Marta Ortín-Obón, Darío Suárez-Gracia, María Villarroya-Gaudó, Cruz Izu, Víctor Viñals-Yúfera

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10.1016/j.micpro.2016.01.005

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Abstract not available

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FPU12/02553

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https://doi.org/10.1016/j.micpro.2016.01.005

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http://hdl.handle.net/2440/97927

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Analysis of network-on-chip topologies for cost-efficient chip multiprocessors

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