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Analysis of network-on-chip topologies for cost-efficient chip multiprocessors

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dc.contributor.authorOrtín-Obón, M.
dc.contributor.authorSuárez-Gracia, D.
dc.contributor.authorVillarroya-Gaudó, M.
dc.contributor.authorIzu, C.
dc.contributor.authorViñals-Yúfera, V.
dc.date.issued2016
dc.description.abstractAbstract not available
dc.description.statementofresponsibilityMarta Ortín-Obón, Darío Suárez-Gracia, María Villarroya-Gaudó, Cruz Izu, Víctor Viñals-Yúfera
dc.identifier.citationMicroprocessors and Microsystems, 2016; 42:24-36
dc.identifier.doi10.1016/j.micpro.2016.01.005
dc.identifier.issn0141-9331
dc.identifier.issn1872-9436
dc.identifier.orcidIzu, C. [0000-0002-7492-8886]
dc.identifier.urihttp://hdl.handle.net/2440/97927
dc.language.isoen
dc.publisherElsevier
dc.relation.grantFPU12/02553
dc.rights© 2016 Elsevier B.V. All rights reserved.
dc.source.urihttps://doi.org/10.1016/j.micpro.2016.01.005
dc.subjectInterconnection networks; Chip multiprocessor; Topology; Mesh; Torus; Ring
dc.titleAnalysis of network-on-chip topologies for cost-efficient chip multiprocessors
dc.typeJournal article
pubs.publication-statusPublished

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