FPGA implementation of a single channel GPS interference mitigation algorithm

Date

2004

Authors

Bucco, G.
Trinkle, M.
Gray, D.
Cheuk, W.

Editors

Wang, J.

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Conference paper

Citation

Proceedings of the International Symposium on GPS/GNSS 2004 / University of New South Wales, Australia, pp. 1-13 [CDROM]

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Gabriel Bucco, Matthew Trinkle, Doug Gray and Wai-Ching Cheuk

Conference Name

International Symposium on GPS/GNSS (2004 : University of New South Wales, Australia)

Abstract

The FPGA (Field-Programmable Gate Array) implementation of an adaptive filter for narrow band interference excision in Global Positioning Systems is described. The algorithm implemented is a Delayed LMS (Least Mean Squares) adaptive algorithm improved by incorporating a leakage factor, rounding and constant resetting of the filter weights. This was necessary as the original adaptive algorithm had stability problems : the filter weights did not remain fixed, and tended to drift until they overflowed, causing the filter response to degrade. Each model was first tested in Simulink, implemented in VHDL (Verilog Hardware Description Language) and then downloaded to an FPGA board for final testing. Experimental measurements of anti jam margins were obtained.

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