FPGA implementation of a single channel GPS interference mitigation algorithm

Simple item page
dc.contributor.authorBucco, G.
dc.contributor.authorTrinkle, M.
dc.contributor.authorGray, D.
dc.contributor.authorCheuk, W.
dc.contributor.conferenceInternational Symposium on GPS/GNSS (2004 : University of New South Wales, Australia)
dc.contributor.editorWang, J.
dc.date.issued2004
dc.description.abstractThe FPGA (Field-Programmable Gate Array) implementation of an adaptive filter for narrow band interference excision in Global Positioning Systems is described. The algorithm implemented is a Delayed LMS (Least Mean Squares) adaptive algorithm improved by incorporating a leakage factor, rounding and constant resetting of the filter weights. This was necessary as the original adaptive algorithm had stability problems : the filter weights did not remain fixed, and tended to drift until they overflowed, causing the filter response to degrade. Each model was first tested in Simulink, implemented in VHDL (Verilog Hardware Description Language) and then downloaded to an FPGA board for final testing. Experimental measurements of anti jam margins were obtained.
dc.description.statementofresponsibilityGabriel Bucco, Matthew Trinkle, Doug Gray and Wai-Ching Cheuk
dc.identifier.citationProceedings of the International Symposium on GPS/GNSS 2004 / University of New South Wales, Australia, pp. 1-13 [CDROM]
dc.identifier.urihttp://hdl.handle.net/2440/28489
dc.language.isoen
dc.publisherGNSS
dc.publisher.placeCD-ROM
dc.relation.ispartofProceedings of GNSS 2004
dc.source.urihttp://www.gmat.unsw.edu.au/gnss2004unsw/GRAY,%20Doug%20P80.pdf
dc.subjectGPS, FPGA, Interference Mitigation, Adaptive filters
dc.titleFPGA implementation of a single channel GPS interference mitigation algorithm
dc.typeConference paper
pubs.publication-statusPublished

Files

Collections

Electrical and Electronic Engineering publications