Current studentsExisting staffContact us
 

Optimal memory size formula for moving-average digital phase-locked loop

Simple item page
dc.contributor.authorAhn, C.
dc.contributor.authorShi, P.
dc.contributor.authorHyun You, S.
dc.date.issued2016
dc.description.abstractThis letter proposes a new moving-average form of digital phase-locked loop (DPLL) that uses the average value of measurements on a memory horizon and the correction term to estimate phase information. This ensures the desired unbiasedness property for the phase information. A new formula for the optimal memory size of the proposed DPLL with minimization of the expected squared phase error is established. A numerical example is given to show that the developed DPLL has superior robustness against quantization and incorrect noise compared to the existing DPLLs.
dc.description.statementofresponsibilityChoon Ki Ahn, Peng Shi, Sung Hyun You
dc.identifier.citationIEEE Signal Processing Letters, 2016; 23(12):1844-1847
dc.identifier.doi10.1109/LSP.2016.2623520
dc.identifier.issn1070-9908
dc.identifier.issn1558-2361
dc.identifier.orcidShi, P. [0000-0001-6295-0405] [0000-0001-8218-586X] [0000-0002-0864-552X] [0000-0002-1358-2367] [0000-0002-5312-5435]
dc.identifier.urihttp://hdl.handle.net/2440/109131
dc.language.isoen
dc.publisherIEEE
dc.relation.grant61573112
dc.relation.grantU1509217
dc.relation.granthttp://purl.org/au-research/grants/arc/DP140102180
dc.rights© 2016 IEEE.
dc.source.urihttps://doi.org/10.1109/lsp.2016.2623520
dc.subjectDigital phase-locked loop (DPLL); moving average; optimal memory size; robustness; unbiasedness
dc.titleOptimal memory size formula for moving-average digital phase-locked loop
dc.typeJournal article
pubs.publication-statusPublished

Files

Collections

Electrical and Electronic Engineering publications