Exploiting concurrency in system-on-chip verification
Date
2006
Authors
Xu, X.
Lim, C.
Editors
Lim, Y.
Advisors
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Conference paper
Citation
IEEE Asia Pacific Conference on Circuits and Systems, 4-7 Dec, 2006:pp.836-839
Statement of Responsibility
Xu, Justin; Cheng-Chew Lim
Conference Name
IEEE Asia Pacific Conference on Circuits and Systems (2006 : Singapore)
Abstract
System-on-chip (SoC) design paradigm makes design verification a more time-consuming task. Therefore, for simulation-based methods, test quality is extremely important. This paper presents a method that increases the test quality by exploiting the concurrency in a system. The main idea is to generalize the elements of concurrency as transfers and then transform the system into a transfer-resource-graph. The graph can be traversed to produce high-quality tests. To further optimize the test quality in terms of concurrency, we are able to generate event-driven test-programs.
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Copyright © 2006 IEEE