Exploiting concurrency in system-on-chip verification

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dc.contributor.authorXu, X.
dc.contributor.authorLim, C.
dc.contributor.conferenceIEEE Asia Pacific Conference on Circuits and Systems (2006 : Singapore)
dc.contributor.editorLim, Y.
dc.date.issued2006
dc.descriptionCopyright © 2006 IEEE
dc.description.abstractSystem-on-chip (SoC) design paradigm makes design verification a more time-consuming task. Therefore, for simulation-based methods, test quality is extremely important. This paper presents a method that increases the test quality by exploiting the concurrency in a system. The main idea is to generalize the elements of concurrency as transfers and then transform the system into a transfer-resource-graph. The graph can be traversed to produce high-quality tests. To further optimize the test quality in terms of concurrency, we are able to generate event-driven test-programs.
dc.description.statementofresponsibilityXu, Justin; Cheng-Chew Lim
dc.identifier.citationIEEE Asia Pacific Conference on Circuits and Systems, 4-7 Dec, 2006:pp.836-839
dc.identifier.doi10.1109/APCCAS.2006.342151
dc.identifier.isbn1424403871
dc.identifier.isbn978-1-4244-0386-8
dc.identifier.orcidLim, C. [0000-0002-2463-9760]
dc.identifier.urihttp://hdl.handle.net/2440/35215
dc.language.isoen
dc.publisherIEEE
dc.publisher.placeCDROM
dc.relation.granthttp://purl.org/au-research/grants/arc/LP0454838
dc.source.urihttps://doi.org/10.1109/apccas.2006.342151
dc.titleExploiting concurrency in system-on-chip verification
dc.typeConference paper
pubs.publication-statusPublished

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