Threshold logic parallel counters for 32-bit multipliers
Date
2002
Authors
Celinski, P.
Cotofana, S.
Abbott, D.
Editors
Harvey, E.C.
Abbott, D.
Varadan, V.K.
Abbott, D.
Varadan, V.K.
Advisors
Journal Title
Journal ISSN
Volume Title
Type:
Conference paper
Citation
Smart structures, devices, and systems : 16-18 December 2002, Melbourne, Australia / Erol C. Harvey, Derek Abbott, Vijay K. Varadan (eds.), pp. 205-214
Statement of Responsibility
Peter Celinski, Sorin D. Cotofana, and Derek Abbott
Conference Name
International Symposium on Smart Materials, Nano- and Micro-Smart Systems (2002 : Melbourne, Australia)
Abstract
In recent years, there has been renewed interest in Threshold Logic (TL), mainly as a result of the development of a number of successful implementations of TL gates in silicon. Threshold Logic enables, in some instances, the design of digital integrated circuits with a significantly reduced transistor count and area. This paper addresses the important problem of designing technologically feasible parallel (m,n) counters for using TL for binary multiplication. A number of counter design techniques are reviewed and some novel parallel counter designs are presented that allow the design of area efficient 32-bit multiplier partial product reduction circuits.
School/Discipline
Dissertation Note
Provenance
Description
© 2003 COPYRIGHT SPIE--The International Society for Optical Engineering. Downloading of the abstract is permitted for personal use only.