Threshold logic parallel counters for 32-bit multipliers
| dc.contributor.author | Celinski, P. | |
| dc.contributor.author | Cotofana, S. | |
| dc.contributor.author | Abbott, D. | |
| dc.contributor.conference | International Symposium on Smart Materials, Nano- and Micro-Smart Systems (2002 : Melbourne, Australia) | |
| dc.contributor.editor | Harvey, E.C. | |
| dc.contributor.editor | Abbott, D. | |
| dc.contributor.editor | Varadan, V.K. | |
| dc.date.issued | 2002 | |
| dc.description | © 2003 COPYRIGHT SPIE--The International Society for Optical Engineering. Downloading of the abstract is permitted for personal use only. | |
| dc.description.abstract | In recent years, there has been renewed interest in Threshold Logic (TL), mainly as a result of the development of a number of successful implementations of TL gates in silicon. Threshold Logic enables, in some instances, the design of digital integrated circuits with a significantly reduced transistor count and area. This paper addresses the important problem of designing technologically feasible parallel (m,n) counters for using TL for binary multiplication. A number of counter design techniques are reviewed and some novel parallel counter designs are presented that allow the design of area efficient 32-bit multiplier partial product reduction circuits. | |
| dc.description.statementofresponsibility | Peter Celinski, Sorin D. Cotofana, and Derek Abbott | |
| dc.identifier.citation | Smart structures, devices, and systems : 16-18 December 2002, Melbourne, Australia / Erol C. Harvey, Derek Abbott, Vijay K. Varadan (eds.), pp. 205-214 | |
| dc.identifier.doi | 10.1117/12.477382 | |
| dc.identifier.isbn | 0-8194-4730-7 | |
| dc.identifier.issn | 0277-786X | |
| dc.identifier.issn | 1996-756X | |
| dc.identifier.orcid | Abbott, D. [0000-0002-0945-2674] | |
| dc.identifier.uri | http://hdl.handle.net/2440/28408 | |
| dc.language.iso | en | |
| dc.publisher | SPIE | |
| dc.publisher.place | CDROM | |
| dc.relation.ispartofseries | Proceedings of SPIE--the International Society for Optical Engineering ; 4935 | |
| dc.source.uri | https://doi.org/10.1117/12.477382 | |
| dc.title | Threshold logic parallel counters for 32-bit multipliers | |
| dc.type | Conference paper | |
| pubs.publication-status | Published |