Low depth, low power carry lookahead adders using threshold logic
Date
2002
Authors
Celinski, P.
Lopez, J.
Al-Sarawi, S.
Abbott, D.
Editors
Advisors
Journal Title
Journal ISSN
Volume Title
Type:
Journal article
Citation
Microelectronics Journal, 2002; 33(12):1071-1077
Statement of Responsibility
Peter Celinski, Jose F. López, S. Al-Sarawi and Derek Abbott
Conference Name
Abstract
This paper describes a low power threshold logic-gate based on a capacitive input, charge recycling differential sense amplifier latch. The gate is shown to have low power dissipation and high operating speed, as well as robustness under process, temperature and supply voltage variations. This is followed by the main result, which is the development of a novel, low depth, carry lookahead addition scheme based on threshold logic. One such adder is also designed and simulated using the proposed gate.