Low depth, low power carry lookahead adders using threshold logic

dc.contributor.author	Celinski, P.
dc.contributor.author	Lopez, J.
dc.contributor.author	Al-Sarawi, S.
dc.contributor.author	Abbott, D.
dc.date.issued	2002
dc.description.abstract	This paper describes a low power threshold logic-gate based on a capacitive input, charge recycling differential sense amplifier latch. The gate is shown to have low power dissipation and high operating speed, as well as robustness under process, temperature and supply voltage variations. This is followed by the main result, which is the development of a novel, low depth, carry lookahead addition scheme based on threshold logic. One such adder is also designed and simulated using the proposed gate.
dc.description.statementofresponsibility	Peter Celinski, Jose F. López, S. Al-Sarawi and Derek Abbott
dc.description.uri	http://www.elsevier.com/wps/find/journaldescription.cws_home/405904/description#description
dc.identifier.citation	Microelectronics Journal, 2002; 33(12):1071-1077
dc.identifier.doi	10.1016/S0026-2692(02)00112-X
dc.identifier.issn	0026-2692
dc.identifier.issn	1879-2391
dc.identifier.orcid	Al-Sarawi, S. [0000-0002-3242-8197]
dc.identifier.orcid	Abbott, D. [0000-0002-0945-2674]
dc.identifier.uri	http://hdl.handle.net/2440/2446
dc.language.iso	en
dc.publisher	Elsevier Sci Ltd
dc.source.uri	https://doi.org/10.1016/s0026-2692(02)00112-x
dc.title	Low depth, low power carry lookahead adders using threshold logic
dc.type	Journal article
pubs.publication-status	Published

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