Using genetic evolutionary software application testing to verify a DSP SoC
Date
2008
Authors
Cheng, A.
Lim, C.
Sun, Y.
He, H.
Zhou, Z.
Lei, T.
Editors
Osseiran, A.
Advisors
Journal Title
Journal ISSN
Volume Title
Type:
Conference paper
Citation
Proceedings of DELTA 2008, 4th IEEE International Symposium on Electronic Design, Test & Applications, 23-25 January, 2008: pp.20-25
Statement of Responsibility
Adriel Cheng, Cheng-Chew Lim, Yihe Sun, Hu He, Zhixiong Zhou, Ting Lei
Conference Name
IEEE International Symposium on Electronic Design (4th : 2008 : Hong Kong)
Abstract
A digital signal processor (DSP) system-on-chip (SoC) can be designed using a variety of architectures and techniques. This often presents different verification challenges compared to conventional SoC or processor designs. Verification of such designs should take into account the goals and applications of the DSP, and how they are eventually used. This paper proposes an application based verification methodology and demonstrates this technique on a real-life DSP SoC design. Our technique employs a library of specially devised application functions as test building blocks, followed by a genetic evolutionary test generator to compose these application functions into effective test programs.
School/Discipline
Dissertation Note
Provenance
Description
Copyright © 2008 IEEE