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Using genetic evolutionary software application testing to verify a DSP SoC

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dc.contributor.authorCheng, A.
dc.contributor.authorLim, C.
dc.contributor.authorSun, Y.
dc.contributor.authorHe, H.
dc.contributor.authorZhou, Z.
dc.contributor.authorLei, T.
dc.contributor.conferenceIEEE International Symposium on Electronic Design (4th : 2008 : Hong Kong)
dc.contributor.editorOsseiran, A.
dc.date.issued2008
dc.descriptionCopyright © 2008 IEEE
dc.description.abstractA digital signal processor (DSP) system-on-chip (SoC) can be designed using a variety of architectures and techniques. This often presents different verification challenges compared to conventional SoC or processor designs. Verification of such designs should take into account the goals and applications of the DSP, and how they are eventually used. This paper proposes an application based verification methodology and demonstrates this technique on a real-life DSP SoC design. Our technique employs a library of specially devised application functions as test building blocks, followed by a genetic evolutionary test generator to compose these application functions into effective test programs.
dc.description.statementofresponsibilityAdriel Cheng, Cheng-Chew Lim, Yihe Sun, Hu He, Zhixiong Zhou, Ting Lei
dc.identifier.citationProceedings of DELTA 2008, 4th IEEE International Symposium on Electronic Design, Test & Applications, 23-25 January, 2008: pp.20-25
dc.identifier.doi10.1109/DELTA.2008.31
dc.identifier.isbn9780769531106
dc.identifier.orcidLim, C. [0000-0002-2463-9760]
dc.identifier.urihttp://hdl.handle.net/2440/49685
dc.language.isoen
dc.publisherIEEE
dc.publisher.placeUSA
dc.relation.granthttp://purl.org/au-research/grants/arc/LP0454838
dc.source.urihttp://www2.computer.org/portal/web/csdl/doi/10.1109/DELTA.2008.31
dc.titleUsing genetic evolutionary software application testing to verify a DSP SoC
dc.typeConference paper
pubs.publication-statusPublished

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